The present invention relates to computer processing, and more specifically, to program counter (PC) relative addressing in a reduced instruction set computing (RISC) instruction set architecture (ISA).
Many RISC architectures do not have a PC-relative addressing mode. PC-relative addressing specifies an address for an instruction that is a defined offset from a current instruction and pointed to by the program counter or instruction address register. PC-relative addressing may be used to load an address of the data item (PC+offset) or load the data item itself by specifying the location of the data item (e.g., a number of bytes ahead of or behind the instruction). RISC architectures are limited in the size of the offset the architecture can employ. The offset may be limited to 16 bits, but at least a 32 bit offset is often needed.
One workaround is to use an add shifted immediate instruction. This command adds a 16-bit immediate value to the upper 16 bits of a 32-bit register, or to bit positions 32 to 47 of a 64-bit register (using big-endian bit numbering of the 64-bit register). Therefore, a 32-bit offset computation is performed in two steps instead of one step, by first adding a set of immediate bits that are shifted and added to compute high-order bits of an offset, and then adding a second set of immediate bits representing the low-order bits of the computed offset. However, this is an expensive solution because it adds an additional operation.
Another workaround involves the use of an extra register that points directly to the data, so that the data is only a small offset away from the register. However, this requires the cost of initializing an extra register. Addressing data using a PC-relative addressing mode, i.e., computing a data address as PC+offset, is more efficient than using an extra register.
One difficulty in using PC-relative addressing is that a very wide bus is needed to transfer a 64-bit address from the instruction fetch and decode unit, where the PC and offset values are available, to the units where the address is to be used. Not only do the 64 bits of the address need to be transferred, but also the displacement that is added to the address needs to be transferred. The total data transferred could be up to 96 bits. Additionally, the PC value must be transferred from an instruction fetch address register (IFAR) or equivalent at one end of the processing pipeline to execution units (such as a fixed point unit (FPU) or load store unit (LSU)) for computing a PC-relative address at another end of the processing pipeline. Transferring a 64 to 96 bit value across this distance is an expensive, difficult, and slow solution.